Improvements in semiconductor technology and semiconductor manufacturing are the main drivers to the reduction of cost and the increase in speed of computers. There have been many advances for increasing the speed of semiconductor devices, ranging from packaging of integrated circuits ("chips") to the wiring of the devices on the chip, to the devices themselves.
Improvements in chip manufacturing techniques include new processes (or improving an existing process) for making the chip. Such improvements may include new, faster and more efficient ways of creating the necessary device structures. For example, many techniques have been developed for forming silicide regions for integrated device contacts, particularly for metal-oxide-semiconductor (MOS) devices formed on silicon substrates. Most of these techniques involve the formation of a metal layer over a gate, drain or source region upon which the silicide is desired to be formed. These techniques then use a thermal treatment to react the metal with the silicon composing the gate, drain and/or source regions, to form the low-resistivity silicide regions. The substrate is further processed by removing the unreacted metal layer, then forming an electrically-insulating layer over the substrate, and finally forming conductive metal lines on the insulating layer. These metal lines can contact the silicide regions over the gate, source and drain regions to form the desired circuit connections for an integrated MOS device.
Techniques for forming suicides are subject to several stringent process constraints that must be met in order for such techniques to be effective. These constraints include: (1) the metal used to form the silicide must be carefully selected to be a species that diffuses into the silicon, to avoid the formation of leakage paths between the source, drain and gate of an integrated device; (2) for self-aligned silicidation techniques, the metal layer must not react with the insulative material composing the self-aligning side walls of the gate; (3) the dopants must not segregate into the silicide regions, which makes it difficult to achieve low contact resistance; (4) the technique should have a process window that allows the silicide region to be formed on both crystalline-silicon and poly-silicon; (5) the silicide formation should be insensitive to dopants present in the silicon; and (6) the metal atoms should not diffuse beyond the suicide regions, that is, into the silicon. If metal atoms diffuse into the silicon, junction leakage will likely increase. The simultaneous fulfillment of all of the above-stated criteria is at best difficult for most conventional silicidation techniques, especially those that use relatively extensive thermal treatments. Most often, a failure to perform the conventional technique within its relatively narrow process margins manifests itself as defects due to thermal drift of the metal atoms beyond desired boundaries during the relatively prolonged thermal treatment periods. If the silicide region extends beyond its design dimensions, it can result in-leakage paths between the gate and the source and drain. Therefore a great need exists for a technique that enhances silicidation process margins beyond those conventionally available.
U.S. Pat. No. 5,888,888 (the '888 patent) discloses a method of producing a silicide region on a Si substrate. The '888 patent is incorporated herein by reference. The method disclosed in the '888 patent is useful for a variety of purposes, including the reduction of the electrical contact resistance to the Si substrate or an integrated electronic device formed thereon. The method includes the step of irradiating a metal layer formed atop the source and drain regions with front side irradiation i.e., irradiating the metal layer from the front side of the silicon substrate to initiate diffusion of the metal into the silicon substrate. While this method is very useful, it would still be preferable to be able to heat the metal layer by other means that result in quicker silicidation.